The present invention relates to a multi-output converter having a plurality of output circuits and, more particularly, to a multi-output converter capable of stabilizing the output voltages of output circuits by changing the switching frequency of a switching device, a conduction duty cycle, and a resonance frequency of particular one of the output circuit.
To better understand the present invention, a brief reference will be made to a conventional multi-output converter, shown in FIG. 1. As shown, a DC voltage source 6 generates a DC voltage Vi while a capacitor 7 bypasses an AC component appearing on the output of the source 6. A field effect transistor (FET) 63 produces an AC component from the DC voltage Vi by a switching operation. This AC component is fed to a first to a third output circuit 200b, 300c and 400c through a transformer 64. The output circuits 200b to 400c may each be replaced with a voltage conversion circuit for converting the DC voltage Vi to another DC voltage, e.g., a forward converter or a flyback converter. Also, the FET 63 may be replaced with an IGBT (Insulating Gate Bipolar Transistor).
In the first output circuit 200c, diodes 9 and 10 belonging to a group of one-way elements rectify the AC component from the transformer 64. An inductor 11, a capacitor 12 and a filter (FIL) 13 smooth the rectified output of the diodes 9 and 10 in cooperation. As a result, an output voltage Vo1 appears between terminals 201 and 202. The voltage on the output of the inductor 11 (substantially equal to the output voltage Vo1) is divided by resistors 35 and 36 included in an error voltage detecting circuit 600a. The divided voltage is applied to one input of an error amplifier 40 which receives a reference voltage Vr1 at the other input. The error amplifier 40 amplifies a difference between the divided voltage and the reference voltage Vr1 and feeds the output thereof to a pulse width modulator 65. The pulse width modulator 65 controls the duration of conduction of the FET 63 by a pulse width corresponding to the output of the error amplifier 40. Specifically, when the output voltage Vo1 of the first output circuit 100b is high, the pulse width modulator 65 delivers to the gate electrode of the FET 63 a control voltage having a pulse width which reduces the duration of conduction of the FET 63. By such control over the FET 63, the output voltage Vo1 is stabilized.
The second output circuit 300c has diodes 16 and 17 which rectify the AC component from the transformer 64. An inductor 18, a capacitor 19 and a filter (FIL) 20 cooperate to smooth the rectified output of the diodes 16 and 17. An output voltage Vo2 appears between terminals 301 and 302. It is to be noted that the voltage on the output of the inductor 18 is an unstable voltage and is stabilized by a triterminal regulator 62 inserted between the inductor 18 and the filter 20 to a predetermined voltage (substantially equal to the output voltage Vo2).
The third output circuit 400c has diodes 26 and 27 for rectifying the AC component from the transformer 64. An inductor 28, a capacitor 29 and a filter (FIL) 30 smooth the rectified output. As a result, an output voltage Vo3 appears between terminals 401 and 402. The voltage on the output of the inductor 28 is also unstable and is stabilized by a triterminal regulator 61 interposed between the inductor 28 and the filter 30 to a predetermined voltage (substantially equal to the output voltage Vo3).
FIG. 2 shows another prior art multi-output converter essentially similar to the circuitry of FIG. 1 except that the second and third output circuits 300c and 400c are replaced with slightly modified second and third output circuits 300d and 400d, respectively.
Specifically, the second output circuit 300d differs from the corresponding circuit 300c in that the triterminal regulator 62 is removed, and in that a control circuit 70b, a diode 80 and a saturable reactor 79 are provided. The control circuit 70b controls, in response to the voltage on the output of the inductor 18 and via the diode 80, the reset current of the saturable reactor 79 connected between the secondary winding of the transformer 64 and the input of the diode 16 so as to change the voltage blocking period of the reactor 79 which corresponds to the reset current period. As a result, the control circuit 70b stabilizes the output voltage Vo2. The control circuit 70b includes resistors 75 and 76 for dividing the voltage on the output of the inductor 18, an error amplifier 73 for generating an error output from the divided voltage and a reference voltage Vr from a reference voltage source 74a, and a transistor 71 and a resistor 72 for amplifying the error output and applying the amplified error output to the diode 80.
The third output circuit 400d is similar to the corresponding circuit 400c except that the triterminal regulator 61 is removed, and in that a control circuit 70a, a diode 78 and a saturable reactor 77 are provided. The control circuit 70a controls, in response to the voltage on the output of the inductor 28 and via the diode 78, the reset current of the saturable reactor 77 connected between the secondary winding of the transformer 64 and the input of the diode 2 so as to change the voltage blocking period of the reactor 77 which corresponds to the reset current period. By such control, the control circuit 70a stabilizes the output voltage Vo3. The control circuit 70a includes resistors 75 and 76 for dividing the voltage on the output of the inductor 28, an error amplifier 73 for producing an error output from the divided voltage and a reference voltage Vr3 from a reference voltage source 74b, and a transistor 71 and a resistor 72 for amplifying the error output and feeding the resulting output to the diode 78.
Referring to FIG. 3, still another prior art multi-output converter will be described which is disclosed in U.S. Pat. No. 5,070,294. As shown, a DC voltage Vi whose AC component has been bypassed appears on opposite ends of a DC voltage source 6 and a capacitor 7. A switching device 110a includes an FET 1 for turning on and turning off the conduction of the DC voltage Vi, and a diode 3 for causing a reverse current to flow which will be blocked by the FET 1. By a switching operation, the switching device 110 produces an AC component from the DC voltage Vi. A resonance circuit 120 includes a series connection of an inductor 4 and a capacitor 5 and provides the AC component from the switching device 110a with a sinusoidal waveform at the junction of the drain of the FET 1 and an inductor 4. The switching device 110a and resonance circuit 120 constitute a resonance switching circuit 100a in combination. Opposite ends of the capacitor 5 are connected to the primary winding of a transformer 8 included in a first output circuit 200. Opposite ends of the series connection of the inductor 4 and capacitor 5 are connected to the primary winding of a transformer 15 included in a second output circuit 300e. The resonance switching circuit 100a and first output circuit 200 arranged in a pair and the second output circuit 300e may each be replaced with a voltage conversion circuit for converting the DC voltage Vi to another DC voltage, e.g., a forward converter or a flyback converter. Also, an IGBT or similar switching element may be substituted for the FET 1.
The first output circuit 200 has diodes 9 and 10 for rectifying the AC component from the secondary winding of the transformer 8. An inductor 11, a capacitor 12 and a filter (FIL) 13 cooperate to smooth the rectified output. As a result, an output voltage Vo1 appears between terminals 201 and 202. Resistors 35 and 36 are included in an error voltage detecting circuit 600 to divide the voltage on the output of the inductor 11. The divided voltage is applied to one input of an error amplifier 40 which receives a reference voltage Vr1 at the other input. The error amplifiers 40 amplifies the difference between the divided voltage and the reference voltage Vr1 and delivers the output thereof to a modulating circuit 500. The modulating circuit 500 turns on and turns off the conduction of the FET 1 by a modulation (switching) frequency matching the output of the error amplifier 40. Assume that the modulation frequency is lower than the fixed resonance frequency of the resonance switching circuit 100a. When the output voltage Vo1 is lower than desired one, the modulating circuit 500 increases the modulation frequency and, therefore, the conduction duty of the FET 1, thereby raising the output voltage Vo1. Conversely, when the output voltage Vo1 is high, the circuit 500 reduces the modulation frequency and, therefore, the conduction duty of the FET 1 so as to lower the output voltage Vo1.
In the conventional converters shown in FIGS. 1 and 2, the resistors 35 and 36, reference voltage source 39 and error amplifier 40 are used to stabilize the output voltage Vo1 of the first output circuit 200b by controlling the duration of conduction of the FET 63. In the conventional circuitry of FIG. 3, they control the modulation frequency of the FET 1 so as to stabilize the output voltage Vo1.
The second output circuit 300e rectifies the AC component from the transformer 15 by diodes 16 and 17, smooths the rectified output by an inductor 18, a capacitor 19 and a filter (FIL) 20, thereby producing an output voltage Vo2 between terminals 301 and 302. Resistors 37 and 38 are included in an error voltage detecting circuit 600 to divide the voltage on the output of the inductor 18. The divided voltage is applied to one input of an error amplifier 41 whose other input is connected to a reference voltage source Vr1. The error amplifier 41 amplifiers the difference between the divided voltage and the reference voltage Vr1 and feed the output thereof to the modulating circuit 500. The modulating circuit 500 controls the duration of conduction (ON) of the FET 1 by a pulse width matching the output of the error amplifier 41. Specifically, when the output voltage Vo2 of the second output circuit 300e is higher than predetermined one, the modulating circuit 500 applies to the gate electrode of the FET 1 a control voltage having a pulse width which reduces the duration of conduction of the FET 1, thereby stabilizing the output voltage Vo2.
The first-described conventional converter stabilizes the output voltage of each of the second and third output circuits by use of a triterminal regulator. This brings about a drawback that a great loss particular to the triterminal regulator not only lowers the power transforming efficiency but also results in the need for a radiator, heat sink or similar cooling part usually associated with a converter. The cooling part undesirably increases the overall size of the converter. Moreover, the accuracy of the output voltage and stability of the converter is determined solely by the triterminal regulator and cannot be freely set.
The second-described conventional converter needs further extra parts, e.g., transistors and resistors for driving the saturable reactor. Moreover, since these parts, including the saturable reactor, bring about losses and, therefore, degrade, the power transforming efficiency. In addition, as the switching frequency of the converter increases, the losses increase the loss of the saturable reactor. This prevents the switching frequency from being increases and, therefore, prevents the converter from being reduced in size. Further, since the saturable reactor has influence on the primary side of the transformer, it is apt to cause the converter to oscillate.
The third-described conventional converter is capable of stabilizing the output voltages of two output circuits by subjecting a single switching device to frequency modulation and pulse modulation. However, the converter cannot stabilize the output voltages of a third and successive converters which may be additionally incorporated. Should the stabilizing circuitry using a triterminal regulator and a saturable reactor be applied to the third and successive output circuits, the problems discussed in relation to the first- and second-described converters would also arise.